Recently,　Graph　Attention　Networks　(GATs)　have　shown　good　performance　for　representation　learning　on　graphs.　Furthermore,　GAT　leverage　the　masked　self-Attention　mechanism　to　get　a　more　advanced　feature　representation　than　the　graph　convolution　networks　(GCNs).　However,　GAT　incurs　large　amounts　of　irregularity　in　computation　and　memory　access,　which　prevents　the　efficient　use　of　traditional　neural　network　accelerators.　Moreover,　existing　dedicated　GAT　accelerators　demand　high　memory　volumes　and　are　difficult　to　implement　onto　resource-limited　edge　devices.　Due　to　this,　this　paper　proposes　an　FPGA-based　accelerator,　called　H-GAT,　which　achieves　excellent　performance　on　acceleration　and　energy　efficiency　in　GAT　inference.　HGAT　decomposes　GAT　operation　into　matrix　multiplication　and　activation　function　unit.　We　first　design　an　effective　and　fully-pipelined　PE　for　sparse　matrix　multiplication　(SpMM)　and　dense　matrix-vector　multiplication　(DMVM).　Moreover,　we　optimize　the　softmax　data　flow　so　that　the　computational　efficiency　of　softmax　can　be　improved　dramatically.　We　evaluate　our　design　on　Xilinx　Kintex-7　FPGA　with　three　popular　datasets.　Compared　to　existing　CPU,　GPU,　and　state-of-The-Art　FPGA-based　GAT　accelerator,　H-GAT　can　achieve　speedup　by　up　to　585×,　2.7×,　and　11×　and　increases　power　efficiency　by　up　to　2095×,　173×,　and　65×,　respectively.　©　2023　Authors.　All　rights　reserved.