Routability　has　always　been　a　very　challenging　issue　in　Very　Large　Scale　Integrated　(VLSI)　circuit　design.　The　routability　is　considered　in　track　assignment　so　that　the　global　routing　results　can　better　match　the　requirements　of　detailed　routing.　However,　existing　heuristic　track　assignment　algorithms　are　prone　to　local　optimality,　which　cannot　provide　the　accurate　routability　estimation.　To　overcome　this　limitation,　we　propose　a　scalable　parallel　Integer　Linear　Programming　(ILP)-based　track　assignment　algorithm,　called　SPTA,　which　employs　a　two-stage　partition　strategy.　First,　by　taking　into　account　both　the　global　and　local　nets,　all　wires　are　assigned　to　tracks,　making　full　use　of　the　information　from　the　global　routing　results.　Second,　an　efficient　ILP　model　for　track　assignment　is　proposed　to　minimize　the　overlap　between　iroutes1,　thus　significantly　improving　routability.　Third,　a　two-stage　partition　strategy　is　designed　to　reduce　the　runtime.　Finally,　a　panel-subpanel-level　parallelism　is　proposed　to　further　speed　up　the　algorithm　without　sacrificing　the　quality　of　the　solutions.　Experimental　results　show　that　SPTA　has　a　better　routability　estimation　compared　with　the　existing　algorithms.　©　2022　IEEE.