Placement　is　a　critical　step　in　the　modern　VLSI　design　flow,　as　it　dramatically　determines　the　performance　of　circuit　designs.　Most　placement　algorithms　estimate　the　design　performance　with　a　half-perimeter　wirelength　(HPWL)　and　target　it　as　their　optimization　objective.　The　wirelength　model　used　by　these　algorithms　limits　their　ability　to　optimize　the　internal　routing　topology,　which　can　lead　to　discrepancies　between　estimates　and　the　actual　routing　wirelength.　This　paper　proposes　an　analytical　placement　algorithm　to　optimize　the　internal　routing　topology.　We　first　introduce　a　differential　wirelength　model　in　the　global　placement　stage　based　on　an　ideal　routing　topology　RSMT.　Through　screening　and　tracing　various　segments,　this　model　can　generate　meaningful　gradients　for　interior　points　during　gradient　computation.　Then,　after　global　placement,　we　propose　a　cell　refinement　algorithm　and　further　optimize　the　routing　wirelength　with　swift　density　control.　Experiments　on　ICCAD2015　benchmarks　show　that　our　algorithm　can　achieve　a　3%　improvement　in　routing　wirelength,　0.8%　in　HPWL,　and　23.8%　in　TNS　compared　with　the　state-of-the-art　analytical　placer.　On　industrial　benchmarks,　our　algorithm　can　also　achieve　a　10.6%　improvement　in　routing　wirelength,　27.3%　in　WNS,　and　34.4%　in　TNS.