The　very　large-scale　integrated　circuit　(VLSI)　placement　problem　is　to　determine　the　exact　location　of　each　movable　circuit　element　within　a　given　region.　It　is　a　crucial　process　in　physical　design,　since　it　affects　performance,　power　consumption,　routability,　and　heat　distribution　of　a　design.　In　this　paper,　we　propose　a　VLSI　placement　flow　to　handle　the　large-scale　mixed-size　placement　problem.　The　main　idea　of　our　placement　flow　is　using　a　floorplanning　algorithm　to　guide　the　placement　of　circuit　elements.　It　consists　of　four　steps:　(1)　With　the　multilevel　framework,　circuit　elements　are　clustered　into　blocks　by　recursively　partitioning;　(2)　a　floorplanning　algorithm　is　performed　on　every　level　of　the　blocks;　(3)　the　macro　cells　are　shifted　by　a　macro　shifting　technique　to　determine　their　exact　locations;　(4)　with　each　macro　cell　location　fixed,　a　standard　cell　placement　algorithm　is　applied　to　place　the　remaining　objects.　The　proposed　approach　is　tested　on　the　IBM　mixed-size　benchmarks　and　the　modern　mixed-size　(MMS)　placement　benchmarks.　Experimental　results　show　that　our　approach　outperforms　the　state-of-the-art　placers　on　the　solution　quality　for　most　of　the　benchmarks.