Graph　convolution　networks　(GCN)　have　demonstrated　success　in　learning　graph　structures;　however,　they　are　limited　in　inductive　tasks.　Graph　attention　networks　(GAT)　were　proposed　to　address　the　limitations　of　GCN　and　have　shown　high　performance　in　graph　-based　tasks.　Despite　this　success,　GAT　faces　challenges　in　hardware　acceleration,　including:　1)　The　GAT　algorithm　has　difficulty　adapting　to　hardware;　2)　challenges　in　efficiently　implementing　Sparse　matrix　multiplication　(SPMM);　and　3)　complex　addressing　and　pipeline　stall　issues　due　to　irregular　memory　accesses.　To　this　end,　this　paper　proposed　SH-GAT,　an　FPGA-based　GAT　accelerator　that　achieves　more　efficient　GAT　inference.　The　proposed　approach　employed　several　optimizations　to　enhance　GAT　performance.　First,　this　work　optimized　the　GAT　algorithm　using　split　weights　and　softmax　approximation　to　make　it　more　hardware　-friendly.　Second,　a　load　-balanced　SPMM　kernel　was　designed　to　fully　leverage　potential　parallelism　and　improve　data　throughput.　Lastly,　data　preprocessing　was　performed　by　pre　-fetching　the　source　node　and　its　neighbor　nodes,　effectively　addressing　pipeline　stall　and　complexly　addressing　issues　arising　from　irregular　memory　access.　SH-GAT　was　evaluated　on　the　Xilinx　FPGA　Alveo　U280　accelerator　card　with　three　popular　datasets.　Compared　to　existing　CPU,　GPU,　and　state-of-the-art　(SOTA)　FPGA-based　accelerators,　SH-GAT　can　achieve　speedup　by　up　to　3283x,　13x,　and　2.3x.